Services include architecture, coding, simulation, testbench generation, test generation, regression testing, synthesis, placement & routing, and
lab testing with customer engineers. Customers can select any of these
services depending on their requirements.

Architecture

Architecture work includes targeting a device family, defining tentative
pinouts, and defining the overall architecture and blocks within the
device.

Coding

The coding phase includes generating commented code under a revision
control system and includes coding from scratch, bug fixes, performance
enhancements and feature addition. Coding may include special code used only during simulation to assert specific invariants, which if violated,
will generate suitable error messages. This might include format
violations on the inputs or between blocks or detection of illegal states.

Testbench Generation

Testbench generation includes device input stimulus from human readable
data files and device output capture and storage into data files in human
readable form. The stimulus could include upstream device simulation and
the output may be passed through simulated downstream devices prior to the testbench monitor. The monitor functions include an input "golden" file
and an output error file. The monitor writes the data out and compares
the data from the device with the golden file saving differences to the
error file. The monitor can also check for specific errors in the output
stream, such as CRC, to simplify error detection. Test benches can be
generated that allow the simulation to be connectioned to software device
drivers through bus models. Also, systems containing microprocessors
with suitable models available can be used to test the hardware and the
software even before actual hardware is available.

Test Generation

With a proper testbench, a series of tests can be devised to test
that all the device features and functionality work correctly based
on the customer specifications. Development of a good test suite with
high feature coverage drastically reduces the time spent in the lab
debugging. Simulation allows full visibility into all of the device
signals aiding debugging and insuring that the actual cause is found
and corrected.

Regression Testing

With a test suite in place, regression testing using that suite allows
bug fixes, performance enhancement, and new features to be added with a
high degree of confidence that no existing functionality is unknowingly
broken by the changes. The suite, based on scripts, is kicked off in
background and the result of each test, pass or fail, is saved in a log
file. Individual tests that fail can be examined later.

Synthesis, Place and Route, and Lab testing

The synthesis and place and route tools along with various other timing
and placement tools are used to achieve cost/density or timing goals
depending on customer requirements. Timing analysis with configuration
options and source code changes are used to achieve the required timing.
Final conversion of the result to files suitable for programming the
devices or for programming the FPGA PROMs completes the process allowing
final testing with the customer for their particular application.

Language Experience:

• Verilog
• VHDL
• PIC
• ABEL
  

FPGA Experience:

• Xilinx
• Altera
• Orca
  

Chip Experience:

• FPGAs
• CPLDs
• PLDs
• PLAs
• ASICs
  

Simulators, Synthesis, And Other Tools:

• Model Technologies (verilog and VHDL)
• ISE
• CoreGen
• FPGA Editor
• Timing Analyzer
• Verilog XL
• Signal Scan
• Altera Max Plus
• VCS
• VCSI
• Concept
• RCS
• SCCS

Capability

Testimonials

Also See:

Device Driver Development

Embedded and DSP Development

ECTF etMerge/CTMedia Development

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